Pythagoreas adder or solid state resolver

ABSTRACT

A system for providing the square root of the sum of the squares of two input signals which can also be used to extract the common carrier component of the sin and cos output windings of a synchro differential resolver. Each input signal is applied to a divider means and to a multiplier means. The output of the divider means constitutes the other input to the multiplier means, and the output of both multiplier means are fed to an adder. The output of the adder constitutes the other input to the divider means. In addition, the output of the adder constitutes the square root of the sum of the squares of the two input signals or the common carrier component of the sin and cos output windings of a synchro differential resolver - depending on the application.

Denoncourt et al.

[ 1 June 20, 1972 [54] PYTHAGOREAS ADDER. OR SOLID 3,495,078 2/1970 James et al. ..235/ 189 STATE RESOLVER P E E G B rimary xaminerugene otz [72] Inventors: Gilles J. llenoncourt, Anjou, Quebec; Assistant E i j Smith Pte tr T.dNe edly, Montreal, Quebec, both Attorney Nei1 McDermid o ana a [73] Assignee: Canadian Marconi Company, Montreal, ABSTRACT Quebec Canada A system for providing the square root of the sum of the [22] Filed: Sept. 30, i969 squares of two input signals which can also be used to extract the common carrier component of the sin and cos output [2] 1 App! 862344 windings of a synchro differential resolver, Each input signal is applied to a divider means and to a multiplier means. The out- [30] Foreign Application Priority Data at of the divider means constitutes the other in ut to the mulp fb h 1 p f 1 tiplier means, and the output 0 0t multip ier means are e Oct. 9, 1968 Canada ..O32,096 E an adder. The output of the adder constitutes the other 52 I U S Cl 235/192 235/186 235/189 input to the divider means. In addition, the output of the adder 5 1 1 lrit. Cl. ..G 06g 7/22 constitutes the Square the Sum Squares 58 Field of Search ..235/184, 186 189, 191, 192 input Signals Carrier comment and 235/i935, 194, 6 cos output windings of a synchro differential resolver densys m aih emfisaqa. 7.- v. [56] References Cited UNITED STATES PATENTS 2 Claims, 4 Drawing Figures 3,493,737 2/1970 Edelson "235/189 "wwmwmww 7' i i V II l2 o V Sm 9 V Sm 9 L 1 X V1 V Sm 9 V1=V [$lN 9+C0S 9] V Cos 9 15222 X M 20 V1 V| Patented June 20, 1912 3,671,731

4 Sheets-Sheet 5 IO c V SIN 9 v sm 9 l2 DEMODULATOR k FILTER ADDER v cos e FILTER 3| a2 SAWTOOTH GENERATOR '1 mm L COMPARATOR m 9 MARK SPACE RATIO CQMPARATOR :cos a- MARK SPACE RATIO ru-m INVENTORS G. .I. DENONCOUR' P T. NEJ EDLY PA TENT AGENTS Patented June 20, 1972 3,671,731

4 Sheets-Sheet 4.

TIME

FIGURE 4 I INVENTORS G. J. DENONCOURT P.'T. NEJEDLY PA TEN T AGENTS PYTIIAGOREAS ADDER R SOLID STATE RESOLVER This invention relates to electronic means for providing the square root of the sum of the squares of two input signals. More specifically, this invention relates to electronic means for extracting the common carrier component of the sin and cos output windings of a synchro differential resolver to thereby provide useful outputs related to the sin and cos functions of the angle whose sin and cos are represented by electrical signals as relative amplitudes on the output windings of the synchro differential resolver.

In electronic navigation systems, it is often necessary to utilize, for example, the sin and cos functions of the angle between desired track and track made good. Thus, it may be necessary to compute the along and across track speed or distance from the heading angle and ground speed as sensed by a Doppler sensor. The sin and cos functions of the angle between desired track and track made good may be derived with a synchro differential resolver by feeding the sensed track angle to one input winding of a synchro and the desired track angle on the shaft of the same synchro. As is well known, the output of the synchro will be the sin and cos functions of the angle between desired track and track made good superimposed on a common carrier (usually the 400 Hz supply).

The functions are represented by the relative amplitudes of the electrical signal across the three-wire or four-wire output windings of the synchro. The three-wire output can be easily converted to the more useful four-wire output by means of a Scott T" transformer.

Although the output signals carry the sin and cos information, they are not individually useful as the common carrier component is dependent on the line voltage. For computation purposes, this common carrier component must be extracted and stored. The instant invention can advantageously be used to carry out this function although the use of the invention is not restricted to the carrying out of this function.

One method for retrieving the common carrier amplitude is described by Hermann Schmid in an article in Electronics, Jan. 10, I966, titled Integrated Circuit Replace Electromechanical Resolver. The accuracy of the system described in this article is limited by the number of components used in that, the greater the number of operational amplifiers, precision resistors and capacitors a circuit consists of, the less accuracy that can be expected.

It is an object of the instant invention toprovide a simple electronic means for providing as one output the square root of the sum of the squares of two input signals.

It is a further object of the invention to provide electronic circuit means for extracting the common carrier component of the sin and cos output windings of a synchro differential resolver to thereby provide useful outputs related to sin and cos functions of the angle whose sin and cos are represented by electrical signals as relative amplitudes on the output windings of the synchro differential resolver.

According to the invention, a circuit for providing the square root of the sum of the squares of two input signals comprises first and second divider means each having output means and first and second input means; first and second multiplier means each having output means and first and second input means; adder means having output means and first and second input means; means for applying one of said input signals to the first input means of said first divider means and to the first input means of said first multiplier means; means for applying the other input signal to the first input means of said second divider means and to the first input means of said second multiplier means; means connecting the output of said first divider means to the second input means of said first multiplier means; means connecting the output of said second divider means to the second input means of said second multiplier means; means connecting the output of said first multiplier means to the first input means of said adder means; means connecting the output of said second multiplier means to the second input means of said adder means; and means connecting the output of said adder means to each of said second inputs of said first and second divider means; whereby the signal at the output of the adder means is representative of the square root of the sum of the squares of the input signals.

In a preferred embodiment of the invention, one input signal is derived from the sin output winding of a synchro differential; and the other input signal is derived from the cos winding of the synchro differential; whereby the signal at the output of said first divider means is representative of the sin function and the signal at the output of the second divider means is representative of the cos function.

The invention will be better understood by reference to the following description together with the accompanying drawings in which:

FIG. 1 illustrates one embodiment of the invention in block diagram form;

FIG. 2 shows a block diagram of a system which can be utilized to extract the common carrier component of a synchro differential resolver output in accordance with the invention;

FIG. 3 illustrates a practical system for extracting the common carrier of a synchro differential resolver output in accordance with the invention; and

FIG. 4 is a graph provided to aid in the explanation of the operation of the comparator in FIG. 3.

Referring now to FIG. 1, two input signals V, and V, are applied from terminals 10 and 20 respectively to dividing means 11 and 21 and also, on separate conductors, multiplication 'means 12 and 22 respectively. The multiplication means 12 and 22 are fed at their second inputs from divider means I1 and 21 respectively. The outputs of the multiplication means are fed to the two inputs of adder means 30, and the output of the adder means is fed, by two separate paths, to the second inputs of divider means 11 and 21.

As can be seen, the output of the adder means, V

2 2 is equal to s t at vs=vs+vs an a 1 v2 Thus, the o u'tpiit'at terrninal 3i seqsai to thesquare raster the sum of the squares of the input signals.

In figure 2, the inputs at terminals 10 and 20 are the signals on the output windings of a synchro differential resolver, V sin0 and V cos0, where V is the common carrier amplitude component. Like numerals refer to like parts in FIGS. 1 and 2. As can be seen, the output of the adder means 30 V1 is equal to V2 m w 2 =3 or V 2 0.4a M

so that V V, i.e., the vector sum of 'VsinO and VcosO. Accordingly, the common carrier amplitude component may be obtained at terminal 31. Again, as V V,, the output at terminal 13 is the sin function and the output at terminal 23 is the cos function.

FIG. 3 illustrates a practical embodiment of the invention. The V sin!) and V cosfl outputs of the synchro differential resolver are fed to demodulators l0 and 20 respectively, and the outputs of the demodulators are DC signals proportional in amplitude to the applied AC signals. Comparator means 11 and 21 correspond to the divider means in FIGS. 1 and 2 while switch means 12 and 22, correspond to the multiplication means. Although in the embodiment illustrated in FIG. 3, switching transistors are shown, it will be apparent that other electronic switch means could be used. Filter means 14 and 24 convert the pulse output of switches 12 and 22 respectively to DC levels, while sawtooth generator 32 produces a linear sawtooth whose amplitude is related to the amplitude at the output of adder means 30.

In operation, the output of the sawtooth generator is fed as one input to both the comparator means 11 and 21, the other input to the comparator means being the DC outputs of the appropriate demodulator means. The sawtooth generator may provide a triangular signal as shown in FIG. 4, in which case the comparators are arranged to provide a zero output when the sawtooth amplitude is greater than the V sinO or V cos0 input, and to provide a positive output when the VsinO or V cos!) input is equal to or greater than the sawtooth amplitude.

FIG. 4 shows the inputs to either of the comparators in a preferred embodiment of the invention. 100 is the output of the appropriate demodulator and 200 is the output of the sawtooth generator. The pulse length at the output of the comparator is proportional to the time interval A-B. Thus, if the output of a demodulator is increased (an increase in the angle size will increase the output of demodulator but decrease the output of demodulator to 100", the pulse length, determined by the interval A"B", is increased, and if the output of the demodulator is decreased, the pulse length is decreased. Thus, the output of the comparators are square waves whose mark/space ratio is proportional to sin0 or cost) so that, in effect, the V cos0 and V sinfi DC levels are divided by the V level of the sawtooth generator.

The outputs of the comparators are fed to the bases of transistors 12 and 22. As these transistors are NPN types, they will be turned on only when a positive signal is applied to the base so that the signals at the collectors of the transistors are multiplied by the mark/space ratio at the output of the comparators, and the inputs to filters l4 and 24 are square waves which, by virtue of a combination of their amplitudes and mark/space ratios, are proportional to V sin() and V cosO respectively. Filters 14 and 24 convert these square waves to DC levels which are then summed in adder 30 to provide an amplitude proportional to the common carrier component V.

Thus, the sin6 and c050 functions are available at terminals 13 and 23 respectively, and the common carrier component may be taken off at terminal 31.

Although several embodiments have been described in the foregoing, this was for the purpose of illustrating, but not limiting, the invention. Various modifications which will come readily to the mind of one skilled in the art are considered to be within the scope of the invention.

We claim:

1. In a circuit for providing the square root of the sum of the squares of two input signals, one of said input signals being derived from the sin output winding of a synchro differential and the other of said input windings being derived from the cos output winding of a synchro differential, comprising: first and second divider means each having output means and first and second input means; first and second multiplier means each having output means and first and second input means; adder means having output means and first and second input means; means for applying one of said input signals to the first input means of said first divider means and to the first input means of said first multiplier means; means for applying the other input signal to the first input means of said second divider means and to the first input means of said second multiplier means; means connecting the output of said first divider means to the second input means of said first multiplier means; means connecting the output of said second divider means to the second input means of said second multiplier means; means connecting the output of said first multiplier means to the first input means of said adder means; means connecting the output of said second multiplier means to the second input means of said adder means; and means connecting the output of said adder means to each of said second inputs of said first and second divider means; whereby the signal at the output of the adder means is representative of the square root of the sum of the squares of the input signals and the signal at the output of said first divider means is representative of the sin function and the signal at the output of the second divider means is representative of the cos function; characterized in that said divider means comprise comparator means and said multiplier means comprise switch means; and further comprising first and second demodulator means; said first demodulator means being connected in circuit between said sin winding of said synchro differential and said first comparator means; and said second demodulator means being connected in circuit between said cos winding of said synchro differential and said second comparator means; first and second filter means; said first filter means being connected in circuit between said first switch means and said adder means; and said second filter means being connected in circuit between said second switch means and said adder means; and a sawtooth generator connected in circuit between said adder means and first and second comparator means.

2. A circuit as defined in claim 1 wherein said first and second switch means comprise first and second transistors each having base, emitter and collector electrodes, the output of said first demodulator means being connected to the collector of said first transistor, the output of said second demodulator means being connected to the collector of said second transistor, the output of said first comparator being connected to the base of said first transistor, the output of said second comparator being connected to the base of said second transistor, the input of said first filter means being connected to the emitter of said first transistor, and the input of said second filter being connected to the emitter of said second transistor. 

1. In a circuit for providing the square root of the sum of the squares of two input signals, one of said input signals being derived from the sin output winding of a synchro differential and the other of said input windings being derived fRom the cos output winding of a synchro differential, comprising: first and second divider means each having output means and first and second input means; first and second multiplier means each having output means and first and second input means; adder means having output means and first and second input means; means for applying one of said input signals to the first input means of said first divider means and to the first input means of said first multiplier means; means for applying the other input signal to the first input means of said second divider means and to the first input means of said second multiplier means; means connecting the output of said first divider means to the second input means of said first multiplier means; means connecting the output of said second divider means to the second input means of said second multiplier means; means connecting the output of said first multiplier means to the first input means of said adder means; means connecting the output of said second multiplier means to the second input means of said adder means; and means connecting the output of said adder means to each of said second inputs of said first and second divider means; whereby the signal at the output of the adder means is representative of the square root of the sum of the squares of the input signals and the signal at the output of said first divider means is representative of the sin function and the signal at the output of the second divider means is representative of the cos function; characterized in that said divider means comprise comparator means and said multiplier means comprise switch means; and further comprising first and second demodulator means; said first demodulator means being connected in circuit between said sin winding of said synchro differential and said first comparator means; and said second demodulator means being connected in circuit between said cos winding of said synchro differential and said second comparator means; first and second filter means; said first filter means being connected in circuit between said first switch means and said adder means; and said second filter means being connected in circuit between said second switch means and said adder means; and a sawtooth generator connected in circuit between said adder means and first and second comparator means.
 2. A circuit as defined in claim 1 wherein said first and second switch means comprise first and second transistors each having base, emitter and collector electrodes, the output of said first demodulator means being connected to the collector of said first transistor, the output of said second demodulator means being connected to the collector of said second transistor, the output of said first comparator being connected to the base of said first transistor, the output of said second comparator being connected to the base of said second transistor, the input of said first filter means being connected to the emitter of said first transistor, and the input of said second filter being connected to the emitter of said second transistor. 